Computer Networks Answers

 Explain how traceroute works. Include a traceroute to a host at least 8 hops away?

Consider that R1 and R2 both are 8 bit registers and contains 11110000 and 00110110 respectively. What will be the values of select inputs, carry-in input and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro operation you may assume the initial value of R1 and R2 as given above)

(i) Decrement R1

(ii) Add R1 and R2 with carry

(iii)AND R1 and R2

(iv) Shift right R1

Assume that a disk has 512 tracks, with each track having 128 sectors and each sector is of size 8 M bits. The cluster size in this system can be assumed to be as 8 sectors. A file having the name assignmentofsemester1.txt is of size 512 MB. Assume that disk has 128 free - continuous clusters. How can this file be allotted space on the disk? Also show the content of FAT after the space allocation to this file. You may make suitable assumptions.

Questions:

1.List down the different between IPv4 and IPv6 address?

2.Cite a situation in which you can apply the knowledge about IPv4 and IPv6 addressing.

Questions:

1.What is the importance of knowing the OSI layers?

2.Cite situation in which you can apply the knowledge of the different OSI layers.

CIDR -A router has the following (CIDR) entries in its routing table:

<span style="font-size:12.0pt; font-family:&quot;Times New Roman&quot;,serif;mso-ascii-theme-font:major-bidi;mso-hansi-theme-font: major-bidi;mso-bidi-theme-font:major-bidi;color:black">Destination Gateway</span>        Next hop

170.46.56.0/21                Interface 1

170.46.48.0/20                 Interface 3

176.53.40.0/22                Router 1

default gateway               Router 2

1. For each of the following IP address, what does the router do if packets with the following addresses arrive?

(a) 170.46.63.10/21

(b) 170.46.67.14/21

(c) 145.46.52.2 /22

(d) 176.53.40.7 /24

(e) 176.53.56.7/24

A router has the following (CIDR) entries in its routing table: Destination Gateway

2. What is the relationship between the “gateway” and “interface” fields?

A computer has 16 MB RAM with each memory word of 32 bits. It has cache memory

having 512 blocks having a size of 128 bits (4 memory words). Show how the main memory

address (CA30FB)h will be mapped to cache address, if

8

(i) Direct cache mapping is used

(ii) Associative cache mapping is used

(iii) Two-way set associative cache mapping is used.

You should show the size of tag, index, main memory block address and offset in your

answer.

The company want each department to have its own subnet. In total, Prime Innovative Technologies CC have 240 employees. Each employee owns a computer. The anticipated growth of the company is to have 2400 employees by the year 2025.

All the employees must be able to communicate with each other within the company. The company’s HQ connects to the company’s ISP.

One of the branches is recommended to make use of a switched local network that have to connect the departments. Within this branch, you are therefore required to make use of VLANs.

As an expert in network administration, you have been hired by this company to design, configure and administer their needs.

Requirements:

1. Utilising Cisco Packet Tracer, design an appropriate detailed network topology for the company.

2. Name the factors that you will take into consideration in designing this network.

3. What are the goals and assumptions of your design?

5. You are required to use routing protocol(s) of your choice.

Assume that a disk has 512 tracks, with each track having 128 sectors and each sector is of size 8 M bits. The cluster size in this system can be assumed to be as 8 sectors. A file having the name assignmentofsemester1.txt is of size 512 MB. Assume that disk has 128 free - continuous clusters. How can this file be allotted space on the disk? Also show the content of FAT after the space allocation to this file. You may make suitable assumptions.

A computer has 16 MB RAM with each memory word of 32 bits. It has cache memory having 512 blocks having a size of 128 bits (4 memory words). Show how the main memory address (CA30FB)h  will be mapped to cache address, if

(i) Direct cache mapping is used

(ii) Associative cache mapping is used

(iii)Two way set associative cache mapping is used.

You should show the size of tag, index, main memory block address and offset in your answer.