Answer to Question #262385 in Computer Networks for Bluwhale

Question

A computer has 16 MB RAM with each memory word of 32 bits. It has cache memory

having 512 blocks having a size of 128 bits (4 memory words). Show how the main memory

address (CA30FB)h will be mapped to cache address, if

8

(i) Direct cache mapping is used

(ii) Associative cache mapping is used

(iii) Two-way set associative cache mapping is used.

You should show the size of tag, index, main memory block address and offset in your

answer.

Answer 1

The memory is Byte- addressable.

Main memory size = 16 MB = 2²⁴ B. That means physical address generated by CPU would be represented

using 24 bits.

Cache memory size = 64 KB = 2¹⁶ B

Block size = 128 B = 2⁴ B. i.e. word would be represented by 8 bits

Therefore, Number of cache lines ÷ blocks = 2¹⁶ ÷ 512 = 2⁷ =128

Since, the cache memory is 4-way set associative.

Hence, number of sets = 2⁷ ÷ 2² = 2⁵   i.e. 6 bits would be required for set/index.

Therefore, Number of bits for tag = 24 – (5 +7) = 12 bits

Hence, the 32 bit address generated by CPU would have following components:

Tag (12 bits)

Set/Index (6 bits)

Word (8 bits)