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1. Determine the Moment of inertia for the singly-symmetrical cross-section 

shown in figure. (5)

2. The thin-walled beam section shown in Figure is subjected to a bending 

moment M applied in a negative sense. Find the position of the neutral 

  • axis and the maximum direct stress in the section.

A bus system that facilitates usage of registers near processor and help in executing instructions properly. Give proper diagram and explain with an example such a system. 


Show the hardware that implements the following statement. Include the logic gates for the
control function and a block diagram for the binary counter with a count enable input.
xyT0 + T1 + y’ T2: AR  AR + 1
A common bus system which is capable of transferring 2 bits at time with number of
registers are 4 each register is of 2 bit? Draw circuit diagram for this and also define how many
multiplexers are required and what will be the size of multiplexer with truth table Also explain
how to gather data from this bus back into register
Starting from an initial value of R in Hex is 47 determine the sequence of binary values in R
after a logical shift-left, followed by a circular shift-right, followed by a logical shift-right and a
circular shift-left. explain through the proper diagrams.

As a designner you have to obtain results using resistors to follow equation :

R3 <- R1 + R2

What would be an appropriate circuit to do so and why


4 A hardware implementation is required for executing the following equations, draw proper diagrams to complete your results. [5 marks] 1- x+y+z+a.b : R3 <- R4-R5 2- a.c.b+d : R3 <- R4+R6


List the limitation of Encoder and explain how this can be rectified by Priority Encoder.

Design a 4:2 Priority Encoder given the priority D3>D1>D0>D2 where all Di’s are input to

the encoder.


As a designer you have to obtain results using registers to following equation:
R3 <- R1+R2
What would be an appropriate circuit to do so and why?
design a bus using multiplexer and demultiplexer where sending processor registers are of 4 bits and receiving memory unit is having two of four bits to store incoming data
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