Engineering Answers

design a bus using multiplexer and demultiplexer where sending processor registers are of 4 bits and receiving memory unit is having two of four bits to store incoming data

As a designner you have to obtain results using resistors to follow equation :

R3 <- R1 + R2

What would be an appropriate circuit to do so and why?

If F1 = ∑m(1,2,4,7) and F2 = ∑m(3,5,6,7), implement them using 3 to 8 line

decoder. Comment on their logic operations.

A hardware implementayion is required for executing the following eqation draw proper diagrams to complete your results x+y+a.b :R3<-R4-R5

Design a bus bus system that can support 4 registers of 2 bits each explain why you create the bus in this method

Explain the methodologies of various type that can be used to manipulate bits in register. Elaborate with proper examples.

Q.1 Design a 6:64 decoder with lower configuration of decoders of your choice, also explain what other possible options can be followed. If the diagram is far big, consider shorthand notations appropriately.[

Q.2 A bus system that facilitates usage of registers near processor and help in executing instructions properly. Give proper diagram and explain with an example such a system.

A hardware implementation is required for executing the following equations , Draw proper diagrams to complete your results ?

1) x+y+z+a.b : R3 <- R4-R5

2) a.c.b+d : R3 <- R4 + R6