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A computer employs RAM chips of 128 x 8 and ROM chips of 512 x 8. The computer system needs 1K bytes of RAM, 2K bytes of ROM, and two interface units, each with two registers. A memory-mapped s 1/0 configuration is used. The two highest-order bits of the 16 bit address bus are assigned 11 for RAM,
10 for ROM, and 01 for interface registers. a. How many RAM and ROM chips are needed?
b. Draw a memory-address map for the system.
c. Give the address range in hexadecimal for RAM, ROM, and interface.
Explain the Comparison of 3 mapping techniques between main memory to cache memory in the tabular form. show how and from where CPU will access the word from the cache memory in each mapping technique with the help of diagram. Take the word number as per your roll no. for example if your roll no is 35 than you have to show how and from where CPU will access W35 from the cache memory in case of each mapping technique with the help of diagram. Assume the main memory size as 16 KB, line size 128 bytes, cache size 1K bytes and k value is 4 .
A virtual memory has a page size of 2K(words). There are eight pages and four blocks. The associative memory page table contains the following entries:
Page Block
0 3
2 1
5 2
6 0
Make a list of all virtual addresses (In decimal) that will cause a page fault if used by the CPU.
Explain set (with 2-set) associative mapping cache. Consider a 4-way set associative mapped cache of size 64 KB with block size 512 bytes. The size of main memory is 256 KB. Finda) Number of bits in tag b) Tag directory size
Consider page reference string of 1 2 3 0 5 0 1 2 1 4 5 0 7 1 2 Using the first in first out (FIFO) page replacement algorithm, draw THREE (3) page frames (3 pages can be in memory at a time during process) for the above-mentioned page reference string. b Calculate the hit rate and fault rate for your answer.
Explain set (with 2-set) associative mapping cache. Consider a 4-way set associative mapped cache of size 64 KB with block size 512 bytes. The size of main memory is 256 KB. Finda) Number of bits in tag b) Tag directory size
Draw the architectural block diagram of ARM and explain data flow referring each unit.
Draw a space-time diagram for a six-segment pipeline showing the time it takes to process eight tasks. Determine the number of clock cycles that it takes to process 200 tasks in a six-segment pipeline.
In certain scientific computations it is necessary to perform the arithmetic operation (Ai + Bi) (Ci + Di) with a stream of numbers. Specify a pipeline configuration to carry out this task. list the contents of all registers in the pipeline for i = 1 through 6.
Explain the Advantages and disadvantages of 3 mapping techniques between main memory to cache memory in the tabular form. show how and from where CPU will access the word from the cache memory in each mapping technique with the help of diagram. Take the word number as per your roll no. for example if your roll no is 35 than you have to show how and from where CPU will access W35 from the cache memory with the help of diagram. Assume the main memory size as 8 KB, line size 128 bytes, cache size 2 K bytes and k value is 2 .
