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A common bus system which is capable of transferring 8 bits at time with number of registers are 4 and each register is of 8 bits? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table
A common bus system which is capable of transferring 8 bits at time with number of registers are 4 and each register is of 8 bits? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table.
fi (0,0) = f (0, 1) = f (1.1) = 1; fi (1,0) = 0
Assuming complements of A and B are not available, what will be the minimum cost solution for realizing using only 2-input NOR gates and 2-input OR gates (each having unit cost)? Explain with nessessary digram and expression.
(a) Connect two conductors to the sheath. Measure the capacitance, Cd between the remaining
single conductor and the two other conductors and the sheath. Take the capacitance between
the shorted cores and the sheath as Cb. Now determine the effective capacitance of each
conductor to the grounded neutral.
(b) A 61800 V concentric cable with two intersheaths has a core diameter of 2.8cm; dielectric
material of 3.8mm thickness constitutes three zones of insulation. Determine the maximum
stress in each of the three layers, if 21800 V is maintained across each of the inner two
layers.
(c) Derive the A, B, C, D constants for two transmission lines connected in parallel.
Suppose 8 bit registers have following contents X=00001111 Y=10101010 Z= 11011011 W=00110011 What will be the 8 bit values of each register after execution of following sequences of microoperations ? X ← 𝑋 + 𝑌 Z←Z⋀ 𝑊, 𝑌 ← 𝑌 + 1 X←X-Z
The outputs of four registers, A, B, C, D, H, L are connected through 8:1 line multiplexer to the input of a fifth register, X. Each register is 16 bits long. The required transfers are dictated by four timing variables, T0 through T3 as follows: T0 : X←A T1 : X←B T2 : X←C T3 : X←D The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the others are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register X.
Design a circuit that would be able to shift bits but also store them for a duration of time. Explain what are the technicalities of such a circuit.
Design a circuit that would be able to shift bits but also store them for a duration of time.
multiplexer to the input of a fifth register, X. Each register is 16 bits long. The
required transfers are dictated by four timing variables, T0 through T3 as follows:
T0 : X←A
T1 : X←B
T2 : X←C
T3 : X←D
The timing variables are mutually exclusive, which means that only one variable is
equal to 1 at any given time, while the others are equal to 0. Draw a block diagram
showing the hardware implementation of the register transfers. Include the
connections necessary from the four timing variables to the selection inputs of the
multiplexers and to the load input of register X.
