Design a bus system that can support 4 registers of 2 bits each. Explain why you created the bus in this method. Also explain how to gather data from this bus back into register.
Explain the methodologies of various type that can be used to manipulate bits in register. Elaborate with proper examples.
Design a 6:64 decoder with lower configuration of decoders of your choice, also explain what other possible options can be followed. If the diagram is far big, consider shorthand notations appropriately.
A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers. a. How many selection inputs are there in each multiplexer? b. What size of multiplexers are needed? c. How many multiplexers are there in the bus? d. Draw the block diagram for this computer common bus system design.
Explain the operation of a JK flipflop with a neat diagram. State how it can be converted into a T (toggle) Flipflop.
If F1 = ∑m(1,2,4,7) and F2 = ∑m(3,5,6,7), implement them using 3 to 8 line
decoder. Comment on their logic operations.
List the limitation of Encoder and explain how this can be rectified by Priority Encoder.
Design a 4:2 Priority Encoder given the priority D3>D1>D0>D2 where all Di’s are input to
the encoder.