Design a bus system that can support 4 registers of 2 bits each. Explain why you created the bus in this method. Also explain how to gather data from this bus back into register.
As shown in the diagram, the most impoirtant lines are S1 and S2 which are jointed to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the bus lines to receive the content of register A since the outputs of this register are connected to the0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.
The following function table shows the register that is selected by the bus for each of the four possible binary values of the Selection lines. With a 4-register system, we can illustrate this as follows:
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