Electrical Engineering Answers

Write a Verilog code for Mealy FSM to detect 0101 sequence with overlapping in behavioral

modeling.

Initialize a 10 bit number “num” of reg data type with a value 0 (i.e. num=10’b0000000000), now

make use of for loop to get the output result as num=10’b001100110011 (Note: It is mandatory to

use for loop for getting this output)

Write a Verilog code for Mealy FSM to detect 0101 sequence with overlapping in behavioral

modeling.

Write a Verilog code for following boolean expression using switch level modeling style.

f(a,b,c)= abc + a + ab

An RL circuit is connected to a 230 V, 50 Hz supply with a rating of 500 VA. If the resistor is 20 Ω, calculate the value of the inductive reactance

A generator is rated 100 MW, 13.8 kV and 90% power factor. The effective resistance is 1.5 times the ohmic resistance. The ohmic resistance is obtained by connecting two terminals to a DC source. The current and voltage are 88.6 A and 4 V, respectively. What is the effective resistance per phase?

Describe how one can adjust the address lines, data

lines, if 4096 bytes of RAM is required by a system.

The lowest chip size is 256*8.

Give complet diagrams.[5 marks]

An extra address space is accocated by the operating 

system to easily run applications . Elaborate on this 

with proper method and strategy of page swapping.[10 marks]

what principles are preferred to bring data into coche,

so that low amount of miss ration is observed ? [5 marks ]

In this method while sending the data towards destination 

a proper method of accepting the data packet is performed.

so, the source knows that data has been revived. Elaborate 

with diagrams and example. [10 marks]