Suppose a computer having 5 GHz processor with cycle time of 4ns and main memory access time
200ns with CPI is 1 cycle.
i. Calculate the processor performance without cache.
ii. Calculate the performance with L1 cache, assume L1 hit rate is 85% and access time is 0.4ns.
iii. Calculate the performance with L2 cache, assume L2 hit rate is 80% and access time is 10ns.
iv. Calculate the performance with L3 cache, assume L3 hit rate is 75% and access time is 10ns.
Consider a computer with the following characteristics: total of 256Mbyte of main memory; block size of 8 bytes; and cache size of 128 Kbytes.
i. Design a direct-mapping address structure.
ii. Design an associative-mapping address structure.
iii. Design a two-way set-associative-mapping address structure.
iv. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache.
v. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag and offset values for a fully-associative cache.
vi. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache set, and word offset values for a two-way set-associative cache.
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