Consider a computer with the following characteristics: total of 256Mbyte of main memory; block size of 8 byte; and cache size of 128 Kbytes.
i. Design a direct-mapping address structure.
ii. Design a associative-mapping address structure. iii. Design a two-way set-associative-mapping address structure.
iv. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache.
v. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag and offset values for a fully-associative cache.
vi. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache set, and word offset values for a two-way set-associative