Part 4 1. Consider the K-Maps given below. For each K- Map i. Write the appropriate standard form (SOP/POS) of Boolean expression. ii. Design the circuit using AND, NOT and OR gates. iii. Design the circuit only by using • NAND gates if the standard form obtained in part (i) is SOP. • NOR gates if the standard form obtained in pat (i) is POS.
Part a) is for the left K-map, Part b) is for the right K-map.
a.
i)
"SOP=A'BC+ABC+AB'C'"
"POS=(A'B'+C')(A'B'+C)(A'B+C')(AB+C')(AB'+C)"
"(A'B'+C')=(A'+C')(B'+C')=(A'+C'+B')(A'+C'+B)\\times"
"\\times (B'+C'+A')(B'+C'+A)=(A'+C'+B')(A'+C'+B))(B'+C'+A)"
"(A'B'+C)=(A'+C)(B'+C)=(A'+C+B)(A'+C+B')\\times"
"\\times(B'+C+A)(B'+C+A')=(A'+C+B)(A'+C+B')(B'+C+A)"
"(A'B+C')=(A'+C')(B+C')=(A'+C'+B)(A'+C'+B')\\times"
"\\times(B+C'+A)(B+C'+A')=(A'+C'+B)(A'+C'+B')(B+C'+A)"
"(AB+C')=(A+C')(B+C')=(A+C'+B)(A+C'+B')\\times"
"\\times(B+C'+A)(B+C'+A')=(A+C'+B)(A+C'+B')(B+C'+A')"
"(AB'+C)=(A+C)(B'+C)=(A+C+B)(A+C+B')\\times"
"\\times(B'+C+A)(B'+C+A')=(A+C+B')(A+C+B')(B'+C+A')"
Standard form:
"POS=(A'+C'+B')(A'+C'+B))(B'+C'+A)(A'+C+B)(A'+C+B')\\times"
"\\times(B'+C+A)(B+C'+A)"
ii)
iii)
SOP using NAND gates:
POS using NOR gates:
b)
i)
"SOP=A'B'C'D'+A'B'CD'+A'BC'D+A'BCD'+ABC'D'+"
"+ABC'D+ABCD+AB'C'D'+AB'C'D+AB'CD+AB'CD'"
"POS=(A'B'+C'D)(A'B'+CD)(A'B+C'D')(A'B+CD)(AB+CD')"
ii)
iii)
SOP using NAND gates:
iii)
POS using NOR gates
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