Consider a memory of 8 words per block. If 2 clock cycle are required to transfer address
from CPU to main memory and 6 clock cycle to access the 1st word and 3 clock cycle each for
consecutive words and 2 clock cycle for transferring the word from memory to cache. Then
calculate the total clock cycle required to transfer the block with interleaving and without
interleaving if the number of module is four.
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