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Explain the operation of a JK flipflop with a neat diagram. State how it can be converted into a T (toggle) Flipflop.
If F1 = ∑m(1,2,4,7) and F2 = ∑m(3,5,6,7), implement them using 3 to 8 line
decoder. Comment on their logic operations.
List the limitation of Encoder and explain how this can be rectified by Priority Encoder.
Design a 4:2 Priority Encoder given the priority D3>D1>D0>D2 where all Di’s are input to
the encoder.
Design a combinational circuit that takes 4-bit binary data as input and generates 2’s
complement of the binary data.
Construct a combinational circuit using 2-input basic gates which has 3 inputs A,B & C
and 3 outputs X,Y &Z. When the decimal equivalent of the binary input is 0, 1, 5 or 3,
the decimal equivalent of the binary output is one greater than the input and when
decimal equivalent of the binary input is 4,2,6 &7 , the decimal equivalent of binary
output is one less than the input.
A common bus system which is capable of transferring 8 bits at time with number of registers are 2 each register is of 8bit? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table Also explain how to gather data from this bus back into register
1) A hardware implementation is required for executing the following equations, draw proper diagrams to complete your results.
1- x+y+z+a.b : R3 <- R4-R5
2- a.c.b+d : R3 <- R4+R6
The 8-bit registers R1, R2, R3, and R4 initially have the following values:
R1-11110010, R2-11111111, R3-10111001 ,R4 11101010
Determine the 8-bit values in each register after the execution of the following sequence of microoperations.
R1 <-R1 + R2
R3<-R3^R4,R2<- R2+1
R1 <- R1 – R3
A common bus system which is capable of transferring 8 bits at time with number of registers are 4 and each register is of 8 bits? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table
