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A hardware implementation is required for executing the following equations, draw
proper diagrams to complete your results. [5 marks]
1- x+y+z+a.b : R3 <- R4-R5
2- a.c.b+d : R3 <- R4+R6

A common bus system which is capable of transferring 4 bits at time with number of registers are 4 each register is of 4 bit? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table Also explain how to gather data from this bus back into register


Show the hardware that implements the following statement. Include the logic gates for the control function and a block diagram for the binary counter with a count enable input. xyT0 + T1 + y’ T2: AR  AR + 1


1) An 8-bit register contains the Hex value 67. What is the register value after an arithmetic shift right? Starting from the initial number 67, determine the register value i) after logical shift right ii) after an arithmetic shift left, and state whether there is an overflow not, explain through the proper diagrams.


 A common bus system which is capable of transferring 8 bits at time with number of registers are 2 each register is of 8bit? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table Also explain how to gather data from this bus back into register 


Determine the true power dissipated in the load of a single-phase bridge rectifier fed from a 220 V 50 Hz supply. The load resistor is equal to the last two numbers of your student number + 10 ohm. 


A bus system that facilitates usage of registers near processor and help in executing instructions properly. Give proper diagram and explain with an example such a system.

A bus system that facilitates usage of registers near processor and help in executing instructions properly. Give proper diagram and explain with an example such a system. 


Show the hardware that implements the following statement. Include the logic gates for the
control function and a block diagram for the binary counter with a count enable input.
xyT0 + T1 + y’ T2: AR  AR + 1
A common bus system which is capable of transferring 2 bits at time with number of
registers are 4 each register is of 2 bit? Draw circuit diagram for this and also define how many
multiplexers are required and what will be the size of multiplexer with truth table Also explain
how to gather data from this bus back into register
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