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 Write a Verilog code for following boolean expression using "switch level modeling style" f(a,b,c)= abc + ac' + ab


"Write a Verilog code for Mealy FSM to detect 0101 sequence with overlapping" in behavioral modeling.


Looking at Run time error, My main field is not c++ computer programming. so mistakes can be occurred.

#include <iostream>

using namespace std;


const int MaxSize = 10;


// Implementation of functions

void insert(float a[], int& n, float x)

{

if (n == 0 || a[n - 1] <= x)

{

a[n] = x;

}

else

{

a[n] = a[n - 1];

int i = n - 1;

insert(a, i, x);

}


if (n < MaxSize)

{

n++;

}

}


int main()

{


float a[MaxSize];

int n = 0;


// Test

float testArray[] = { 20.0, 5.0, 30.0, 50.0, 2.0, 50.5, 25.5, 40.0, 100.0, 80.0, 70.0 };

for (int i = 0; i < 11; i++)

{

insert(a, n, testArray[i]);

}


for (int i = 0; i < n; i++)

{

cout << a[i] << "\n";

}


// To pause

cin.get();

cin.get();


return 0;

}

On my Machine This Program Executes Where the Prototype Occurs and definition occurs.

 regards;

so how to remove run time error.

regards;


Extra address space is allocated by the operating system to easily run application. elaborate on this with proper method and strategy of page swapping?[10 marks]


Principle are performed to bring data into cache, so that low amount of miss ratio is observed?[5marks]


In this method while sending the data towards destination a proper method of accepting that data packet is performed so the source known that the data has been received elaborate with diagram and example.[10 marks]


Both ammeters in the circuit shown in Figure 2 indicate 1.7 A. If the source supplies 300 W to the circuit, find 𝑅1 and 𝑅2.


Based on Figure 3, answer the following questions: (i) Find the Thevenin voltage 𝑉𝑇𝐻 at terminal A-B. (ii) Find the Norton current 𝐼𝑁 at terminal A-B. (iii) Calculate the Norton resistance by using answers from (i) and (ii). (iv) Draw the Thevenin equivalent circuit. 


Design, using SR flip-flops and an external input x, a circuit that will count modulo 10 (i.e. from zero to nine, then back to zero and repeat). The circuit should only count when x = 1. If x = 0, there should be no change of state. Show all the steps involved.

 

a.     Draw the State diagram

b.     From the state diagram, derived the circuit excitation and output/state table

c.     Use K-maps to derive the necessary logic equations for the flip-flop inputs

d.     Draw the sequential circuit.


Design sequential circuit with two JK flip-flops A and B and two inputs E and x. If E = 0 the circuit remains in the same state regardless of the value of x. When Ex = 11; the circuit goes through the transitions from 00 → 01→ 10 → 11 → 00, and repeat. When Ex = 10, the circuit goes through the state transitions from 00 → 11 → 10 → 01 → 00, and repeat. 


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