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We would like to design a synchronous sequential circuit with two inputs A1 and A0, and one output Z. The two inputs are interpreted as a two-bit unsigned integer A1A0. Assume the input combination A1A0 = 11 will never happen. In other words, the inputs represent an integer from 0 to 2. The circuit will produce an output of 1 if the sum of the last two inputs in the input sequence is 2. Draw the state diagram of a Moore-type FSM for the circuit. Draw your diagram as clearly as possible.
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