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Electric Circuits
Calculate the ratio Vc/V at the turn-over frequency (sometimes called the break frequency)
if R1=1kΩ and C=2µF
if R1=1kΩ and C=2µF
Electric Circuits
100Hz square wave is applied to the following circuit. The maximum and minimum values of the signal amplitude is 5V and 0V respectively.
How many time constants would it take for the signal Vc to rise from 0V to 63.2% of 5V?
How many time constants would it take for the signal Vc to rise from 0V to 63.2% of 5V?
Electric Circuits
Two resistors, R1 = 200 Ω and R2 = 800 Ω are connected in series across a d.c. supply, Vs = 20 V
Calculate voltage drop V2 across R2 .
Calculate voltage drop V2 across R2 .
Electric Circuits
Consider a two-input NOR gate. Which of the following inputs to this NOR gate will give an output of Logic 1?
Electric Circuits
Consider a two-input NAND gate. Which of the following inputs to this NAND gate will give an output of Logic 0?
Electric Circuits
Consider the following circuit, that at this point in time, before any more clock pulses are fed to the input, the values of QA, QB, QC and QD are as follows:
0000
What would the values of QA, QB, QC and QD be after another four clock cycles?
0000
What would the values of QA, QB, QC and QD be after another four clock cycles?
Electric Circuits
Consider a D-type flip-flop.
The input to D changes from a logic 1 to a logic 0 just after the falling edge of the clock.
Qn=1 at the time D changes. Which of the following is true?
1.at the falling edge of the clock, Qn+1=0
2.at the falling edge of the clock, Qn+1=1
3.at the rising edge of the clock, Qn+1=0
4.at the rising edge of the clock, Qn+1=1
The input to D changes from a logic 1 to a logic 0 just after the falling edge of the clock.
Qn=1 at the time D changes. Which of the following is true?
1.at the falling edge of the clock, Qn+1=0
2.at the falling edge of the clock, Qn+1=1
3.at the rising edge of the clock, Qn+1=0
4.at the rising edge of the clock, Qn+1=1
Electric Circuits
Consider a J-K flip-flop. J=1, K=1. Which of the following is true?
1.at the falling edge of the clock, Qn+1 is the same logic state as Qn
2.at the falling edge of the clock, Qn+1 is the opposite state of Qn
3.at the rising edge of the clock, is the same logic state as Qn
4.at the rising edge of the clock, Qn+1 is the opposite state of Qn
1.at the falling edge of the clock, Qn+1 is the same logic state as Qn
2.at the falling edge of the clock, Qn+1 is the opposite state of Qn
3.at the rising edge of the clock, is the same logic state as Qn
4.at the rising edge of the clock, Qn+1 is the opposite state of Qn
Electric Circuits
Consider a J-K flip-flop. J=1, K=0. Qn=0. which of the following is true?
1.at the falling edge of the clock, Qn+1=0
2.at the falling edge of the clock, Qn+1=1
3.at the rising edge of the clock, Qn+1=0
4.at the rising edge of the clock, Qn+1=1
1.at the falling edge of the clock, Qn+1=0
2.at the falling edge of the clock, Qn+1=1
3.at the rising edge of the clock, Qn+1=0
4.at the rising edge of the clock, Qn+1=1
Electric Circuits
Consider a J-K Flip flop. You are required to set the output of the flip-flop to a logic 1 irrespective of the values of the inputs to J, K and clock terminals. This needs to be done once only, and then the Flip Flop should be in a state to operate normally.
which of the following will achieve this requirement?
Note: HIGH = 5V, LOW= 0V.
which of the following will achieve this requirement?
Note: HIGH = 5V, LOW= 0V.
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#339914 on Dec 2023
#339914 on Dec 2023