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calculate the total sound pressure level caused by a combination of sounds with the following SPL,s (a) 25db and 39db (b)60db+60db+60db
Sir in my school my physics teacher has given a work to make a praticle file on topic new scientific inventen and forth coming technology. Sir i have no idea to how make a practicle file on this given topic. please help me sir.
What is the maximum reading allowed for earth continuity on a white goods appliance?
many thanks
Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a
clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds.
Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.
(A) I only (B) II only (C) I and III only (D) II and III only (E) I, II, and III
A processor takes 12 cycles to complete an instruction 1. The corresponding pipelined processor uses 6 stages with the execution times of 3, 2, 5, 4, 6 and 2 cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed?

A)1.83

B)2

C)3

D)6
A bus is a set of wires connecting computer components. A computer may have several buses, e.g. a system bus, an internal bus, and special purpose local buses. All communication between the various components takes place over one of these buses. For example, data transfer between the CPU and memory normally occurs on the system bus, while movement of data between registers and the ALU takes place on a bus internal to the microprocessor chip. The speed at which data can be transferred is dependent on the number of data lines in the bus and, in the case of synchronous buses, the clock speed of the bus. The transfer rate or bandwidth of a particular system bus can be calculated from the number of cycles required for transfer, the length of the cycle and the number of data lines. Each data line carries 1 bit at a time.

Suppose that a bus has 16 data lines and requires 4 cycles of 250 ns each to transfer data. The bandwidth of this bus would be,
a)1Mb/s b)2 Mb/s c)4 Mb/s d)8Mb/s
A transducer is isolated from environmental changes so as to reduce the effects of environmental inputs causing errors in measurement is an example of _____ which is one of the compensating method of error correction.
Select one:
a. Compensating non-linear element
b. Differential system
c. Isolation
d. None of these
A communication channel is of 10kbps bandwidth. The transmission media is fiber optic. We need to
send a window of size 15 packets, where each packet is containing 5000bytes. The total time to
transfer all data from one to another node is:
(a) 50ms
(b) 25ms
(c)75ms
(d)None of these
A computer is taking 5 clock cycles if data is present in the cache memory. In all instructions only
30% data are fetched, but miss rate is 10% and CPU gives miss penalty of 10 clock cycles for this.
What will be the gain if all instructions fetched are available in the cache memory?
(a) 5.2
(b) 6.3
(c) 1.79
(d) None of these
Consider a computer system have a processor-X which in general takes 4ns clock cycles but for ALU
branch instruction and memory operation takes 5 clocks cycles and 9 clock cycles, respectively. In
CPU, ALU 80% operations occurred, memory operations 25% occurred, branch instruction 30%
occurred. Other overheads over CPU execution take 1ns. What will be the average instructions
execution time if it is used in un-pipelined processor?
(a) 30ns
(b) 25.4ns
(c)23.4ns
(d)None of these
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