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The 8-bit register AR, BR, CR, and DR initially have the following values: [5]

AR = 11010010;BR = 11111111;CR = 10101001;DR = 10101010

Determine the 8-bit values in each register after the execution of the following sequence of microoperations.

AR <-AR + BR                                              Add BR + AR

CR <- CR AND DR, BR<-BR + 1     AND DR to CR, Increment BR

AR<- AR - CR                                              Subtract CR from AR



A common bus system which is capable of transferring 4 bits at time with number of registers are 4 each register is of 4 bit? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table Also explain how to gather data from this bus back into register.

please also show diagram and truth table


The 8-bit registers AR, BR, CR, and DR initially have the following values:

AR = 11010010;         BR = 11111111;         CR = 10101001;         DR = 10101010

Determine the 8-bit values in each register after the execution of the following sequence of microoperations. 

AR <-AR + BR

CR <- CR ^ DR, BR <- CR + 1

AR <-AR – CR 


Design a circuit that would be able to shift bits but also store them for a duration of time
A common bus system which is capable of transferring 2 bits at time with number of
registers are 4 each register is of 2 bit? Draw circuit diagram for this and also define how many
multiplexers are required and what will be the size of multiplexer with truth table Also explain
how to gather data from this bus back into register [10 marks]
A common bus system which is capable of transferring 8 bits at time with number of
registers are 2 each register is of 8bit? Draw circuit diagram for this and also define how
many multiplexers are required and what will be the size of multiplexer with truth table
Also explain how to gather data from this bus back into register

Show the hardware that implements the following statement. Include the logic gates for the

control function and a block diagram for the binary counter with a count enable input.

xyT0 + T1 + y’ T2: AR  AR + 1


A common bus system which is capable of transferring 2 bits at time with number of

registers are 4 each register is of 2 bit? Draw circuit diagram for this and also define how many

multiplexers are required and what will be the size of multiplexer with truth table Also explain

how to gather data from this bus back into register


Show the hardware that implements the following statement. Include the logic gates for the

control function and a block diagram for the binary counter with a count enable input.

xyT0 + T1 + y’ T2: AR  AR + 1


The 8-bit registers R1, R2, R3, and R4 initially have the following values:

R1 - 1111 0010, R2- 1 1 1 1 1 1 1 1 , R3- 1011 1001 , R4 1 1 101010

Determine the 8-bit values in each register after the execution of the following sequence of

microoperations.

R1 <-R1 + R2

R3<- R3 ^ R4, R2 <- R2 + 1

R1 <- R1 – R3


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