Electrical Engineering Answers

Show the hardware that implements the following statement. Include the logic gates for the

control function and a block diagram for the binary counter with a count enable input.

xyT0 + T1 + y’ T2: AR  AR + 1

A common bus system which is capable of transferring 2 bits at time with number of

registers are 4 each register is of 2 bit? Draw circuit diagram for this and also define how many

multiplexers are required and what will be the size of multiplexer with truth table Also explain

how to gather data from this bus back into register

Show the hardware that implements the following statement. Include the logic gates for the

control function and a block diagram for the binary counter with a count enable input.

xyT0 + T1 + y’ T2: AR  AR + 1

The 8-bit registers R1, R2, R3, and R4 initially have the following values:

R1 - 1111 0010, R2- 1 1 1 1 1 1 1 1 , R3- 1011 1001 , R4 1 1 101010

Determine the 8-bit values in each register after the execution of the following sequence of

microoperations.

R1 <-R1 + R2

R3<- R3 ^ R4, R2 <- R2 + 1

R1 <- R1 – R3

 Starting from an initial value of R in Hex is 47 determine the sequence of binary values in R after a logical shift-left, followed by a circular shift-right, followed by a logical shift-right and a circular shift-left. explain through the proper diagrams. 

A common bus system which is capable of transferring 8 bits at time with number of registers are 2 each register is of 8bit? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table Also explain how to gather data from this bus back into register    

1)    An 8-bit register contains the Hex value A9. What is the register value after an arithmetic shift right? Starting from the initial number A9, determine the register value

 i)        after logical shift right

A common bus system which is capable of transferring 2 bits at time with number of registers are 4 each register is of 2 bit? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table Also explain how to gather data from this bus back into registe