Design the architecture of DMA mode of operation and illustrate how various components
namely, CPU, RAM, DMA Controller and I/O Peripheral interface each other.
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) A 100 MVA, 13.8 kV, 60 Hz, Y-connected 3-phase generator with Xd ’’=Xd ’=20% is connected to a 13.3/220 kV, 100 MVA, ∆-Y connected transformer and to the 3-phase load of 100 MVA 0.8 p.f. lagging is connected to the transformer secondary as shown in the figure. The leakage reactance of ∆-Y transformer is 10%. The L-L voltage at the load Page 5 of 5 terminals is 220 kV. A 3-phase short-circuit occurs at the load terminals. Find the generator transient current including load current.
The unique addresses assigned to the four registers (R11,R12,13,R14) of the I/O interface are equal to the XX3 , XX7 , XXB and XXF in Hex . Where XX is hex digits equal to your roll no . (if student is having roll no 45 than address are 453 ,457 ,45B , 45F in Hex ) .Show the well labeled external circuit that must be connected between and 12-bit I/O address from the CPU and the CS, RSI, and RS0 Inputs of the Interface.
Find the values of the flags (carry ,sign ,zero, overflow) of the processor status register for the given example of two 8 bit no’s in Hex (A7 + EF) and draw the circuit diagram also.
Explain the addressing modes in detail with the help of example of each?
Explain the Memory stack organization of 16 locations of stack( 0 to 15). take the initial value of the stack pointer is SP = 0E in Hex. Explain the following push and pop instructions through the Memory stack organization diagram. (1) PUSH R5 WHERE R5 = XX in Hex (2) POP R4 WHERE R4 = (XX + 3 ) Hex for example roll no 64 is having the data in R5 = 64 Hex and R4 is ( 64+3 = 67 Hex)
Enlist major differences that exist between central computer and the peripheral devices.
What role does an interface play in resolving these differences?
Explain addressing modes in detail with example of each.
Design the architecture of DMA mode of operation and illustrate how various components
namely, CPU, RAM, DMA Controller and I/O Peripheral interface each other.