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A 100-kW, 250-V DC shunt generator has an armature resistance of 0.05Ω. With the generator operating at rated voltage, determine the induced voltage at full load.
All about Logic Circuits
Definition of Logic circuits in less than 10,000 words and maximum of 15,000 words.
Explain the working principal of 4-bit parallel binary adder/subtractor
(Two 4-bit binary numbers inputs)
P2 Activity
P2 Explain and compare the construction and characteristics of a DC motor and a DC generator

Task 4
Using suitable diagrams and pictures explain how a DC motor is constructed and operates, making sure to highlight any key characteristics.

Task 5
Using suitable diagrams and pictures explain how a DC generator is constructed and operates, making sure to highlight any key characteristics.

D1 Activity
D1 Evaluate the need for a DC motor starter and discuss its operation

Task 6
i.) Explain why a DC motor requires a starter in order to operate
ii.) Using relevant diagrams explain how a starter works in a DC motor
iii.) Finally, using your previous answers, evaluate the usefulness for a DC motor starter, making sure to discuss any major limitations or draw backs
Give an example of an embedded computing device. For this device give one example each of
Input and Storage
Mathematical Calculations
Logic (Comparing Values)
Retrieval and Display
Consider a microwave oven as a computing device. For this device give two examples each of:
1:Input and Storage
2:Mathematical Calculations
3:Logic (Comparing Values)
4:Retrieval and Display
Explain two ways in which alternator emf can be increased?
A delta connected three phase transformer of 415V; 50Hz supply has 100 turns on primary winding and 600 turns on secondary winding. Find the output phase voltage and the output phase current if the output is connected to a delta load?
For the unsigned addition of the given bit-pattern pair, identify the overall delay (i.e. the delay at which all the outputs of the circuit are finalized) experienced in the case of each unsigned adder circuit mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in.
0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0
1 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1
i. RCA
ii. CCA
iii. BCLA with block size=8
iv. RCA-BCL adder with block size=8
v. CSA with block size=2
vi. CSelA with block size=8. Assume that the first block is implemented as an RCA
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