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(a) Design a synchronous counter using J-K FFs that has the following sequence: 000, 010, 101, 110, and repeat. The undesired (unused) states 001, 011, 100, and 111 must always go to 000 on the next clock pulse.
(b) Redesign the counter of part (a) without any requirement on the unused states; that is, their NEXT states can be don’t cares. Compare with the design from (a).
A transformation has a voyage 480 V and current 2.5 A on the primary side and 40 V on the secondary . What is the secondary current on the load ?
(i) Find the charge in the volume defined by 0 < y < 2 and 0 < z < 2 , if theVolume charge density is rho_{v} = 60y * z ^ 2 * mu * C / (m ^ 3)
Verify the Stokes's theorem for the following vector F=2 rho z hat a rho +; 3z sin varphi hat a varphi -4 rho cos p hat a z over the range z = 1 , 0< p < 2, 0 < varphi < 45 degrees .

Write Verilog codes of 8-bit Log Left Shifter and 4-bit Barrel Right/Left Shifter.

Simulate the designs with test benches of at least 4 test cases. 


Using boolean algebra, simplify each expression:

_

(B + BC)(B + B^C)(B + D)


Using boolean algebra, simplify the following expression:

_ _

(A + A^)(AB+ABC^)


Using boolean algebra techniques, simplify the following expression as much as possible:

_ _ _ _

ABC+ABC+ABC


Construct a truth table for each for the following boolean expression:

(A+B)C


Draw the logic circuit represented by each of the following expression:

_ _

AB^+A^B


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