Answer to Question #256213 in Electrical Engineering for subin

Question

Design and Implement the following logic functions using Verilog. And must be implemented using all three modeling techniques (Gate level modeling, Dataflow modeling, and Behavioral modeling)

i. Unclocked S-R latch.

ii. Clocked S-R latch.

Answer 1

We do need to implement a total of 5 functions so we need to switch between these functions so we need to use a mux that can accommodate 5 inputs so we would require 8to1 MUX whose first 5 inputs would be the functions we should be implementing and the other can be random and then we have to give the select pins accordingly.

Code :

module ALU(

input a,

input b,

input [2:0]sel,

output reg [1:0] out

);

parameter And=3'b000,Or=3'b001,Add=3'b010,Sub=3'b011,Less=3'b100;

/* code for the MUX along with the functional units describes the whole ALU*/

always @(*)

begin

case(sel)

And: out=a&b;

Or: out=a|b;

Add: out = a+b;

Sub: out = a-b;

Less: out = a<b;

endcase

end

endmodule

Explanation: I have taken a five inputs for the ALU as the output of the functional blocks that were needed to be implemented in the ALU and then I have declared the parameters for the MUX as And which is selected when select lines were 000, Or which is selected when select lines were 001, Add which is selected when select lines were 010, Sub which is selected when 011, Less which is selected when select lines were 100.

TestBench:

module tb_ALU();

reg a,b;

reg [2:0]sel;

wire [1:0]out;

ALU a1(a,b,sel,out);

initial

begin

a=1'b0;

b=1'b0;

sel=3'b000;

#5 a= 1'b1;

b = 1'b1;

sel = 3'b000;

#5 sel = 3'b001;

#5 sel = 3'b010;

#5 sel = 3'b011;

#5 sel = 3'b100;

end

endmodule

Explanation: I have taken both the inputs to be 1,1 and then I have started varying the select lines from 000 to 100 so that we can observe the outputs of every function.

Simulated Waveform:

The type of modeling we have used is Behavioral modeling.