Notably, we see that output 1 of register A is connected to input 0 of MUX 1 because this input is labeled A1 . The diagram shows that the bits in the same significant position in each register are connected to the data inputs of one multiplexer to form one line of the bus. Thus, MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of the registers, and similarly for the other two bits.
This design connection can be shown as captured below:
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