Below figure illustrates the use of 2:1 MUX to generate the logic gates.
AND Gate Truth Table:
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate Truth Table:
A B Output
0 0 0
0 1 1
1 0 1
1 1 1
NAND Gate Truth Table:
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
NOR Gate Truth Table:
A B Output
0 0 1
0 1 0
1 0 0
1 1 0
EXOR Gate Truth Table:
A B Output
0 0 0
0 1 1
1 0 1
1 1 0
NOT Gate
A Output
1 0
0 1
Comments
Leave a comment